3 ms·
> If a chip knows that there is a fixed set of opcodes, it can specialize decoding to only decode the opcodes it knows about. What does that mean? The CPU stil
by colejohnson66 4y ago
> If a chip knows that there is a fixed set of opcodes, it can specialize decoding to only decode the opcodes it knows about.
What does that mean? The CPU still needs to trap on undefined ones. I don't think the spec even allows non-trapping behavior[a]. So there's still some kind of decode happening. And if each instruction is 32 bits, you don't need any logic to find the instruction boundary on an undefined one.
[a]: By "non-trapping", I mean behavior akin to what old processors would do where every opcode would do something because of gaps in the PLAs (such as 0xAF on the 6502 performing 0xAD (LDA abs) and 0xAE (LDX abs) at the same time)
- dzaima 4y agoThe spec contains "The behavior upon decoding a reserved instruction is unspecified." which to me sounds like that the CPU can do whatever it wants.
- colejohnson66 4y agoI stand corrected
- kragen 4y agoThe RISC-V spec does allow non-trapping behavior and SeRV in particular has non-trapping behavior, which is an important part of how it can fit into 200 4-input LUTs. Trap handling is also not part of the base ISA. https://github.com/olofk/serv#good-to-know https://github.com/olofk/serv#good-to-know