That did keep some previous aspects of AMD design, notably subclusters of shared last level cache on a single chip. Zen1 and Zen2 used 4 core clusters of shared

That did keep some previous aspects of AMD design, notably subclusters of shared last level cache on a single chip. Zen1 and Zen2 used 4 core clusters of shared L3, with accesses to the other 4 core cluster requiring a bit more latency as it was going outside of the CCX. Zen3 changed this, so it no longer applies in the same way. The result was some latency graphs such as: https://www.anandtech.com/show/15708/amds-mobile-revival-redefining-the-notebook-business-with-the-ryzen-9-4900hs-a-review/2 https://www.anandtech.com/show/15708/amds-mobile-revival-red...