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> It's clearly a Core derivative with a uop cache, if you look at the overall structure of the pipeline. Er, no. The structure of the pipeline is exactly what

> It's clearly a Core derivative with a uop cache, if you look at the overall structure of the pipeline. Er, no. The structure of the pipeline is exactly what it took from the P4. P6 derivatives, including core, store in-flight results in the ROB, and then write them back to the RRF at retire. RRF read ports are a limited, shared resource, with full throughput only achieved when most instructions get their operands from the ROB. P4 and SNB store only pointers in the ROB, putting all results directly into the PRF, with no work done on retire. The PRF has enough ports to serve all requests. This is an entirely different way to organize the cpu.

bonzini 4y ago
The PRF is what I meant by "the Alpha-like OoO engine". It was not an innovation specific to Netburst, AMD uses it too nowadays and it's not really possible to do otherwise with 256- and 512-bit AVX registers. The structure of the Netburst front end depended heavily on the trace cache while the Sandy Bridge uop cache is more like an "L0" that can miss sometimes. The back end of Sandy Bridge doesn't need the messy replay system that was in Netburst. So this is what I meant by the pipeline being more similar to Nehalem.
n7pdx 4y ago
You are completely over-complicating things. P6 derivatives stuck with “traditional” Tomasulo algorithm for way too long. Everyone else moved to pointers for arch regs long before Intel did: MIPS 10k, DEC, AMD, Intel P4, etc, it isn’t really that big of a deal and is actually a simplification from the design aspect. There hasn’t been a total overhaul of CPU arch in decades. For whatever reason, Intel called this mechanism “marbles”. There are a bunch of names in the industry for this: PRF, arch pointers, etc… its all the same thing. By the way, moving to arch pointers is precisely what adds additional work on retirement: you need to do a walk or checkpoint restore to revert the arch state back to where it needs to be. With P6/Tomasulo, it is free. You got it backwards.

bonzini 4y ago

The PRF is what I meant by "the Alpha-like OoO engine". It was not an innovation specific to Netburst, AMD uses it too nowadays and it's not really possible to do otherwise with 256- and 512-bit AVX registers. The structure of the Netburst front end depended heavily on the trace cache while the Sandy Bridge uop cache is more like an "L0" that can miss sometimes. The back end of Sandy Bridge doesn't need the messy replay system that was in Netburst. So this is what I meant by the pipeline being more similar to Nehalem.

n7pdx 4y ago

You are completely over-complicating things. P6 derivatives stuck with “traditional” Tomasulo algorithm for way too long. Everyone else moved to pointers for arch regs long before Intel did: MIPS 10k, DEC, AMD, Intel P4, etc, it isn’t really that big of a deal and is actually a simplification from the design aspect. There hasn’t been a total overhaul of CPU arch in decades. For whatever reason, Intel called this mechanism “marbles”. There are a bunch of names in the industry for this: PRF, arch pointers, etc… its all the same thing. By the way, moving to arch pointers is precisely what adds additional work on retirement: you need to do a walk or checkpoint restore to revert the arch state back to where it needs to be. With P6/Tomasulo, it is free. You got it backwards.