3 ms·

Afaik its <120KB/s with all the tricks. 6502 was hand designed and brain optimized for clever use of available silicon real-estate, roughly 20% of CPU bus cycle

by rasz 4y ago

Afaik its <120KB/s with all the tricks. 6502 was hand designed and brain optimized for clever use of available silicon real-estate, roughly 20% of CPU bus cycles are dead/bogus/useless. RTS wastes 3 of its 6 cycles, RTI 2 of 6 wasted, JSR 1 of 6 wasted , all increments at least 1 cycle wasted etc. Sad to think state machine handling DMA transfers in REU is probably less than 50 macrocells, and Commodore ran its own fab, they could have build-in REU DMA in C128 and it would cost cents.

mywittyname 4y ago
Is there a way to make a compatible 6502 variant that doesn't have this waste?
- rasz 4y ago
  https://en.wikipedia.org/wiki/CSG_65CE02#Pipeline_improvements https://en.wikipedia.org/wiki/CSG_65CE02#Pipeline_improvemen... fixed most painful ones, but afaik not all dead cycles. But it was 1988 and commodore didnt bother putting it into anything other than some IO card for the AMIGA, not to mention it still did nothing to cover slowness of moving data around. Japanese decided to do something about it for TurboGrafx-16 in 1987 Hu6502 http://shu.emuunlim.com/download/pcedocs/pce_cpu.html http://shu.emuunlim.com/download/pcedocs/pce_cpu.html Transfer Alternate Increment (TAI), Transfer Increment Alternate (TIA), Transfer Decrement Decrement (TDD), Transfer Increment Increment (TII) - pretty much x86 'rep movsb', except not great at 6 cycles per byte (~160KB/s). For contrast 5 years older 80286 already did 'rep movsw' at 2 cycles per byte. 6 years later Pentium did 'rep movsd' at 4 bytes per cycle. Nowadays Cannonlake can do 'rep movsb' full cachelines at a time at full cache/memory controller speed.
  - JPLeRouzic 4y ago
    I think there are tricks to rewrite the microcode on Pentium, does similar tricks exist for 80286, 386 or 68K? It would be fun to reconfigure one as a high speed 6502.
- krallja 4y ago
  “The 100 MHz 6502” does a different clever thing - it copies all the dedicated RAM and ROM into its own FPGA copy. Then it can perform 7 to 25 instructions before the next external read/write cycle! http://www.e-basteln.de/computing/65f02/65f02/ http://www.e-basteln.de/computing/65f02/65f02/

by rasz 4y ago

mywittyname 4y ago

Is there a way to make a compatible 6502 variant that doesn't have this waste?

rasz 4y ago
https://en.wikipedia.org/wiki/CSG_65CE02#Pipeline_improvements https://en.wikipedia.org/wiki/CSG_65CE02#Pipeline_improvemen... fixed most painful ones, but afaik not all dead cycles. But it was 1988 and commodore didnt bother putting it into anything other than some IO card for the AMIGA, not to mention it still did nothing to cover slowness of moving data around. Japanese decided to do something about it for TurboGrafx-16 in 1987 Hu6502 http://shu.emuunlim.com/download/pcedocs/pce_cpu.html http://shu.emuunlim.com/download/pcedocs/pce_cpu.html Transfer Alternate Increment (TAI), Transfer Increment Alternate (TIA), Transfer Decrement Decrement (TDD), Transfer Increment Increment (TII) - pretty much x86 'rep movsb', except not great at 6 cycles per byte (~160KB/s). For contrast 5 years older 80286 already did 'rep movsw' at 2 cycles per byte. 6 years later Pentium did 'rep movsd' at 4 bytes per cycle. Nowadays Cannonlake can do 'rep movsb' full cachelines at a time at full cache/memory controller speed.
- JPLeRouzic 4y ago
  I think there are tricks to rewrite the microcode on Pentium, does similar tricks exist for 80286, 386 or 68K? It would be fun to reconfigure one as a high speed 6502.
krallja 4y ago
“The 100 MHz 6502” does a different clever thing - it copies all the dedicated RAM and ROM into its own FPGA copy. Then it can perform 7 to 25 instructions before the next external read/write cycle! http://www.e-basteln.de/computing/65f02/65f02/ http://www.e-basteln.de/computing/65f02/65f02/