4 ms·
It begs a question though: How many instructions in <insert ISA here> are equivalent? I assume that a compiler writer has a list of equivalents and will typical
by anitil 4y ago
It begs a question though: How many instructions in <insert ISA here> are equivalent? I assume that a compiler writer has a list of equivalents and will typically choose the shorter one?
- icodestuff 4y agoThere are a number of considerations there. Size is only one of them. Speed and internal processor state effects are two others. For instance, a larger, slower instruction might prevent a pipeline stall in a particular function or might enable loop unrolling or might allow a shorter loop unrolling, while in a similar function that doesn’t pipeline the same way, the compiler will choose a faster instruction.
- anitil 4y agoYou're right I completely overlooked pipelining. I guess I'm out of my depth here
- IcePic 4y agoFor RISC ISAs like MIPS, then you can do a lot of ADD Reg0 to Reg0 and store result in Rx OR Reg0 with reg0 and store result in Rx XOR Reg0 with reg0 and .. The only issue is that for RISC, all these instructions are of equal length, so flipping them around would gain you very little, or more likely zero effect unless you are chasing some corner case thing like "XOR instruction value compresses slightly better than ADD because.."