I've got some background in FPGA development, and you can actually design for this effect. We literally have tools where you can plug in simulated activity and

I've got some background in FPGA development, and you can actually design for this effect. We literally have tools where you can plug in simulated activity and the tool will tell you how much dynamic power the chip will use and therefore what power & cooling you'll need. It works exactly as you say - different inputs are going to cause different numbers of transistors to need to switch every cycle and switching draws more power. So if you have a transistor that goes 1->0->1 every other cycle, that'll draw more power than a transistor that's just sitting at 0 the entire time. Then, since modern CPUs have frequency scaling (fpgas generally don't) you can observe that a high switching rate would increase the power consumption which increases the heat and therefore causes the CPU to scale down the frequency.