7 ms·

> This means that, on modern processors, the same program can run at a different CPU frequency (and therefore take a different wall time) when computing, for ex

> This means that, on modern processors, the same program can run at a different CPU frequency (and therefore take a different wall time) when computing, for example, 2022 + 23823 compared to 2022 + 24436. I'm not a hardware expert, and I was a bit surprised at this. Is that because the transistors heat up more with certain input values, which then results in a lower frequency when the CPU gets hot enough? Something like AND(1,1) using more energy than AND(1,0) on the transistor level? As far as I can tell [1], addition typically takes a constant number of cycles on x86 CPUs at least, so any difference should happen at a very low level. [1] https://www.agner.org/optimize/instruction_tables.pdf https://www.agner.org/optimize/instruction_tables.pdf

simias 4y ago
Not an expert either but number of cycles is not everything, transistors that transition use up more energy than those who remain in the same state. As such it's possible that 0x00000000 + 1 uses up significantly less energy than 0xffffffff + 1, just because of all the bit flips. That's just a guess though.
- userbinator 4y ago
  That is exactly the principle behind this. A small quantity of energy needs to be consumed to flip a bit.
SilverBirch 4y ago
I've got some background in FPGA development, and you can actually design for this effect. We literally have tools where you can plug in simulated activity and the tool will tell you how much dynamic power the chip will use and therefore what power & cooling you'll need. It works exactly as you say - different inputs are going to cause different numbers of transistors to need to switch every cycle and switching draws more power. So if you have a transistor that goes 1->0->1 every other cycle, that'll draw more power than a transistor that's just sitting at 0 the entire time. Then, since modern CPUs have frequency scaling (fpgas generally don't) you can observe that a high switching rate would increase the power consumption which increases the heat and therefore causes the CPU to scale down the frequency.

simias 4y ago

Not an expert either but number of cycles is not everything, transistors that transition use up more energy than those who remain in the same state. As such it's possible that 0x00000000 + 1 uses up significantly less energy than 0xffffffff + 1, just because of all the bit flips. That's just a guess though.

userbinator 4y ago
That is exactly the principle behind this. A small quantity of energy needs to be consumed to flip a bit.

SilverBirch 4y ago

I've got some background in FPGA development, and you can actually design for this effect. We literally have tools where you can plug in simulated activity and the tool will tell you how much dynamic power the chip will use and therefore what power & cooling you'll need. It works exactly as you say - different inputs are going to cause different numbers of transistors to need to switch every cycle and switching draws more power. So if you have a transistor that goes 1->0->1 every other cycle, that'll draw more power than a transistor that's just sitting at 0 the entire time. Then, since modern CPUs have frequency scaling (fpgas generally don't) you can observe that a high switching rate would increase the power consumption which increases the heat and therefore causes the CPU to scale down the frequency.