5 ms·

I wonder how they manage that? It's straightforward to do if a page fault represents an error that halts the execution of a thread but not if you need to be ab

I wonder how they manage that? It's straightforward to do if a page fault represents an error that halts the execution of a thread but not if you need to be able to keep going after the OS reads in the data from the hard drive. That is, if you speculatively load values that aren't going to be used in a loop then the fact that you had poisoned values sitting around in some registers doesn't matter. But if that data "should" have been there but wasn't and you store or branch based on it then you've got to roll back to the load, page in the data, then continue from the checkpoint. And if you're able to do all of that why not just go full out of order?

rayiner 4y ago
The pipeline state can be checkpointed with a fixed amount of logic gates that’s proportional to the amount of pipeline state. Out of order execution requires tracking dependencies in structures that scale superlinearly with the size of the out of order window.
- Symmetry 4y ago
  It isn't bound by the pipeline length. Even without pipelining at all, with poisoning you can do a faulting load into a register and then just mark the value in the register as poisoned. As you perform operations with the value any results are also poisoned. Then maybe dozens or hundreds of cycles later when you store or branch on one of the poisoned values the fault occurs. So pipeline length really doesn't have anything to do with it. On Itanium you essentially had to double check your values for poison before operating on them in a lot of cases and that caused big performance penalties on conventional code. Other systems restrict the shenanigans you can get up to with your MMU and solve the problem that way but that means you can't run a traditional OS with mmaped files and memory paging and such. I'm not sure what the Tachyum people are doing or if they've got some clever idea to get around all of this.
avianes 4y ago
I'm not sure if this answers your question but VLIW processors feature speculative loads. "speculative load" can be seen as data prefetch to a register, but with a extra instruction to put before reading/using the register. This instruction check that the memory content has been received, otherwise the instruction stall the pipeline. It allows to reorder a load before a conditional branch. To determine whether the load has been received, there is an additional structure in the microarchitecture that tracks speculative loads in-flight. When a context switch occurs, this data-structure is overwritten, so there are additional mechanisms to replay the load in such cases.

rayiner 4y ago

The pipeline state can be checkpointed with a fixed amount of logic gates that’s proportional to the amount of pipeline state. Out of order execution requires tracking dependencies in structures that scale superlinearly with the size of the out of order window.

Symmetry 4y ago
It isn't bound by the pipeline length. Even without pipelining at all, with poisoning you can do a faulting load into a register and then just mark the value in the register as poisoned. As you perform operations with the value any results are also poisoned. Then maybe dozens or hundreds of cycles later when you store or branch on one of the poisoned values the fault occurs. So pipeline length really doesn't have anything to do with it. On Itanium you essentially had to double check your values for poison before operating on them in a lot of cases and that caused big performance penalties on conventional code. Other systems restrict the shenanigans you can get up to with your MMU and solve the problem that way but that means you can't run a traditional OS with mmaped files and memory paging and such. I'm not sure what the Tachyum people are doing or if they've got some clever idea to get around all of this.

avianes 4y ago

I'm not sure if this answers your question but VLIW processors feature speculative loads. "speculative load" can be seen as data prefetch to a register, but with a extra instruction to put before reading/using the register. This instruction check that the memory content has been received, otherwise the instruction stall the pipeline. It allows to reorder a load before a conditional branch. To determine whether the load has been received, there is an additional structure in the microarchitecture that tracks speculative loads in-flight. When a context switch occurs, this data-structure is overwritten, so there are additional mechanisms to replay the load in such cases.