Indeed, video decode would be offloaded to dedicated silicon blocks on the GPU for video decode (e.g. AMD UVD/VCN or Nvidia NVDEC, etc) rather than running enti

Indeed, video decode would be offloaded to dedicated silicon blocks on the GPU for video decode (e.g. AMD UVD/VCN or Nvidia NVDEC, etc) rather than running entirely on compute blocks. Implementation-wise though, I don’t think hardware decoders would use general purpose CPU cores under the hood (someone correct me if I’m wrong — been a long time since I’ve worked on this stuff), but would use dedicated fixed-function blocks. On hardware without a full fixed-function decode, I would think it would fall back to compute blocks with fixed-function blocks for acceleration. Some other implementations might make use of customized CPU cores like from Tensilica. General purpose CPU cores might instead be used for things like managing HDCP, etc.