4 ms·
> the original cache invalidation problem Do you have any reference or links about it? Thanks. > point of view of a writer in a multiple-writer distributed sy
by uvdn7 4y ago
> the original cache invalidation problem
Do you have any reference or links about it? Thanks.
> point of view of a writer in a multiple-writer distributed system
> If you assume a single-writer, multiple-reader architecture, you don't have the original problem at all.
It starts to sounds like you are describing Paxos?
- tremon 4y agoActually, I was thinking of cache coherency protocols in multi-processor systems like MESIF or MOESI: - https://en.wikipedia.org/wiki/Cache_coherency_protocols_(examples) https://en.wikipedia.org/wiki/Cache_coherency_protocols_(exa... - https://www.cs.utexas.edu/~pingali/CS377P/2018sp/lectures/mesi.pdf https://www.cs.utexas.edu/~pingali/CS377P/2018sp/lectures/me... I know the same problem exists in distributed shared-memory systems like supercomputers, but I'm not sure where the original term comes from. (edit: you can take some comfort that you're not the first to define cache invalidation in this way, but then you're not the first to claim this victory either: https://briandunnington.github.io/distributed_cache_invalidation https://briandunnington.github.io/distributed_cache_invalida... ;)
- uvdn7 4y agoThanks for the links! Yeah I assumed it would originate cache coherency protocol as well. In that case, it's not hard to figure out "when" to invalidate, as you just invalidate the cacheline on mutates based on addresses. If cache invalidation originates from cache coherency protocols, I would assume Phil Karlton's quote was not referring to the "when" to invalidate as being the hard problem. But I will not die on this hill. I am open to rephrase/redefine/reword in anyway that is helpful to people.