You're quite right, a traditional die with 6.8 billion transistors on it would likely have serious yield issues. This is why Xilinx is using the silicon interpo

You're quite right, a traditional die with 6.8 billion transistors on it would likely have serious yield issues. This is why Xilinx is using the silicon interposer to combine multiple die into a single package. So it's not actually 1 6.8b transistor die but 4 roughly 1.7b transistor die. Still huge, but in line with the level of integration that others (Intel, IBM) are using.