3 ms·

There’s also Archipelago: https://www2.eecs.berkeley.edu/Pubs/TechRpts/2014/EECS-2014-43.pdf https://www2.eecs.berkeley.edu/Pubs/TechRpts/2014/EECS-2014-... S

There’s also Archipelago: https://www2.eecs.berkeley.edu/Pubs/TechRpts/2014/EECS-2014-43.pdf https://www2.eecs.berkeley.edu/Pubs/TechRpts/2014/EECS-2014-... Someone could mix a version of that with the open-source RISC-V IP for an open CPU/FPGA combo.

pabs3 4y ago
And eFabless have some sort of open FPGA thing. https://github.com/efabless/clear https://github.com/efabless/clear https://news.ycombinator.com/item?id=30437021 https://news.ycombinator.com/item?id=30437021