A comment and reply from the Reddit thread on r/fpga here - https://www.reddit.com/r/FPGA/comments/uz2u0a/write_synthesizable_verilog_in_c_with_metron/ https://

A comment and reply from the Reddit thread on r/fpga here - https://www.reddit.com/r/FPGA/comments/uz2u0a/write_synthesizable_verilog_in_c_with_metron/ https://www.reddit.com/r/FPGA/comments/uz2u0a/write_synthesi... - "Sounds all very nice, but isn't it just hdl with a C++ syntax then? I am fluent in both C++ and VHDL, but I wouldn't think of trying HDL in C++ because the way of thinking is so different. I can see the purpose of HLS, but if this isn't HLS then what is the purpose?" Yes, it's HDL with a C++ syntax. That's the point. Lower learning curve, easier experimentation, incremental conversion from general-purpose C++ to Verilog-compatible semantics, smaller code, faster simulation, easier debugging, no conversion pass needed for C++ testbenches. Metron source files are plain C++ headers with no special language annotations required, so you can start writing "hardware" without leaving your C++ IDE. The way of thinking is very different, but with Metron you can get from "procedural" C++ to "hardware" C++ incrementally. Metron handles a lot of the plumbing details for you so that your converted modules behave more like C++ classes, though you can fall back to explicit port defintions if you need more control.