4 ms·
^this, there are more layers now, and it's all fairly RISC like at the bottom or so I'm told.
by tomxor 4y ago
^this, there are more layers now, and it's all fairly RISC like at the bottom or so I'm told.
- rcxdude 4y agoThis is a bit of a myth: microcode is used a lot in x86, but a lot of it is for emulating obselete instructions. The vast majority of instructions on x86 are still directly implemented in the hardware (including such decidedly non-RISC instructions as 'take this register, multiply it by 4, add it to this other register, then load that address from memory and do a floating-point multiplication of it with this 3rd register and store the result there', all without any microcode). If anything the RISC side of the coin (ARM) has become much more CISC like over time.
- colejohnson66 4y agoAlso not entirely true. All x86 instructions are translated into an internal microcode/uop format; only the "complex" ones use the "microcode ROM". The execution units don't know what `01 C0` (add eax, eax) means; only the decoder does. The decoder turns those bytes into something like `eax := ADD_DSZ32(eax, eax)` that the execution unit understands. For example, `01 01 00 00` (add [ecx], ebx) is probably translated by the PLAs into 3 uops similar to these: tmp0 := LOAD_DSZ32(ecx) tmp0 := ADD_DSZ32(tmp0, eax) STORE_DSZ32(ecx, tmp0) But any operation requiring four or more uops (such as "complex addressing") would go to either the "long" decoders or the microcode ROM
- tomxor 4y agoOk now I'm confused. Is it possible you are both correct but your understanding are from different points in time where microcode based ops have been used more over time? i.e would the GPs comment be correct for a specific, older generation of intel x86, and yours perhaps be more applicable to newer generations?
- colejohnson66 4y agoMy understanding is: every x86 processor from Intel and AMD has been microcoded to an extent. The 8086 through the 808486 used a "horizontal microcode" PLA (like all microprocessors of the era), but when Intel introduced the first superscalar x86 processor, the P5, they switched to "vertical microcode". IIRC, that vertical microcode has always been based around "simple" decoder PLAs and a "complex" decoder ROM. Horizontal microcode is the execution unit control lines being toggled directly by the PLA. Vertical microcode (of the P5 and up) is more in line with what people understand "microcode" to be, but it's still internal uops, never "raw" x86 instructions. The encoding of the actual uop can usually be roughly correlated with the external ISA encoding, but that's just to ease work on the decoder. Realistically, with CISC, you'll always have a microcode sequencer of some sort. More broadly, short of a TTA, there's going to be a PLA somewhere. [0]: https://en.wikipedia.org/wiki/Transport_triggered_architecture https://en.wikipedia.org/wiki/Transport_triggered_architectu...
- tomxor 4y agoThanks! Strangely I wouldn't have guessed the 8086 had anything resembling microcode, even though when I think about it there are obvious examples of earlier microcoded CPUs - My understanding is definitely too vague, I wasn't even aware of the distinction between horizontal and vertical, thanks for highlighting the depth of this to me.
- colejohnson66 4y agoSure thing! The world of microarchitecture is really interesting IMO.
- userbinator 4y agoIf you're referring to uops, that's closer to VLIW than RISC. AFAIK the whole RISC vs CISC thing has always been more about the software-visible instruction set than the implementation.