Probably a decade or two premature but can't hurt to hedge the bets (there's definitely opportunity to make software that makes fpga and asic compilation from h

Probably a decade or two premature but can't hurt to hedge the bets (there's definitely opportunity to make software that makes fpga and asic compilation from higher level languages easier though - only reason it's not happening is the high talent required and low amount of people at that intersection, there's no way verilog/vhdl is the global minima).