FPGAs aren't meant to be updated live, so it could be used to represent the reptilian brain of the AGI. Or say if FPGAs are faster, more compact, or power effi

FPGAs aren't meant to be updated live, so it could be used to represent the reptilian brain of the AGI. Or say if FPGAs are faster, more compact, or power efficient then the parts of the network that changes slowest could be kept in them to complement the more dynamic parts. I think we still have quite a ways to go before these optimizations since running the network is much easier than training it.