Thanks for the insight. Quite a few things in here I need to read up on. My naïve thought is some "common high level language" would talk down to the Verilog/V

Thanks for the insight. Quite a few things in here I need to read up on. My naïve thought is some "common high level language" would talk down to the Verilog/VHDL or whatever the FPGA language is and hopefully that is dynamic/modifiable on runtime but doesn't seem to be so.