2 ms·
Given how bad the state of FPGA tools are, we'll probably get a super intelligent AGI writing its own self modifying FPGA code before we get good FPGA toolchain
by techdragon 4y ago
Given how bad the state of FPGA tools are, we'll probably get a super intelligent AGI writing its own self modifying FPGA code before we get good FPGA toolchains for the major vendors...
Its nice we have the handful of Lattice chips with open toolchains, but 9 times out of ten people still use other FPGAs for their reference designs unfortunately.
...
Snark aside, FPGAs currently on the market probably can't reprogram while computing (unless its a special hidden feature or something) its not something I've ever seen in documentation that talks about loading the chip configuration at power on time. However at a meta "many FPGA system" level, you could certainly have hardware hot-plug capable systems "offline" a chip unit, reload its code using a hardware management system that looks after this aspect (like using an Lights Out Management system to reboot a racked server in a datacenter)... then power it back up again with the new configuration and it gets added back into the system automatically due to the hot-plug system... so I guess the answer is "yes, but..."
- ge96 4y agoThanks for the insight. Quite a few things in here I need to read up on. My naïve thought is some "common high level language" would talk down to the Verilog/VHDL or whatever the FPGA language is and hopefully that is dynamic/modifiable on runtime but doesn't seem to be so.