> logic doesn't break in the same way source code breaks Uhh, sure it does. Any non-trivial digital hardware design, be it for an ASIC or an FPGA, will contain

> logic doesn't break in the same way source code breaks Uhh, sure it does. Any non-trivial digital hardware design, be it for an ASIC or an FPGA, will contain a lot of state machines interacting with each other, sometimes asynchronously. Hardware isn't immune from reaching a system state which requires a reset of the device.