7 ms·
It's correct. Planes reflect the physical structure of the storage chips: there's multiple layers that share a common vertical bus. Plane > Block > Page, that
by jasonwatkinspdx 4y ago
It's correct.
Planes reflect the physical structure of the storage chips: there's multiple layers that share a common vertical bus.
Plane > Block > Page, that is to say Blocks are always made up of multiple pages (commonly 128 or 256 as the quote mentions). Pages are the unit of read and write, while blocks are the unit of erasure. The FTL tries to hide this page write vs block erase mismatch as best it can, but as the original article points out you may need to be aware of what it's doing in very high performance systems.
- wtallis 4y agoA single NAND die is only divided into two or four planes. It's a function of how many copies of the peripheral circuitry for accessing the array are included, not how many layers are in the 3D NAND array. More planes means the die can do more things in parallel (subject to constraints). A drive with 8 dies each having 512Gbit capacity divided into four planes per die will perform almost as well as one with 16 dies of 256Gbit divided into two planes, other things being equal (eg. number and speed of the channels between the SSD controller and the NAND, page and block sizes and access times, all of which are subject to change at the same time a generational change increases die capacity and number of planes).
- jbverschoor 4y agoOk that makes more sense. A small diagram outlining the 3d structure would be helpful.