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Well the chipset also handles shuttling RAM channels..

• NinjaKitten 4y ago
  No. You appear to have a fundamentally flawed understanding of the system at hand.
  • cududa 4y ago
    Perhaps. 16 years out from AMD ram/ cpu channel optimization. If the chipset isn’t handling RAM channels what component is?
    • wtallis 4y ago
      The DRAM controller has been on the CPU socket since AMD's Opteron/Athlon 64 (2003) and Intel's Nehalem first-gen Core i5/i7 products (2008). AMD's recent migration toward multiple chiplets on the CPU package has not changed the direct connection between DRAM and the CPU socket.
      • Laforet 4y ago
        >AMD's recent migration toward multiple chiplets on the CPU package has not changed the direct connection between DRAM and the CPU socket This is true. However with the MCH off-chip and worst case inter core latency comparable a DRAM refresh cycle, AMD could in theory move the MCH away from the socket and see no major performance penalty. Not to mention the Zen 2 IO die is just a cut-down version of X570, or maybe it is the other way around heh?