Xeon Phi boards with HBM had a few modes of operation. The HBM could act as a cache for main memory, or you could set it up as directly addressable. You could

Xeon Phi boards with HBM had a few modes of operation. The HBM could act as a cache for main memory, or you could set it up as directly addressable. You could then allocate buffers in that address space and know they'd never be evicted. I wonder if it was ever useful though. If you're able to make your algorithms stay within a certain block of memory, just allocating that in main memory and letting the cache do its job would seem to achieve the same goal. I've heard that a frequent complaint with the Phi was that the speedups were absolutely real after code was modified to suit the architecture, but then when the adjusted code was tested on conventional Xeons it was sped up almost as much.