4 ms·
768MB of L3 cache. I'm excited about that, it should be possible to fit kernel / OS / application with enough left over to handle streaming data from ram.
by JonChesterfield 4y ago
768MB of L3 cache. I'm excited about that, it should be possible to fit kernel / OS / application with enough left over to handle streaming data from ram.
- nynx 4y agoWhat ends up in what cache needs to be programmable in the same way as ram and storage.
- reitzensteinm 4y agoXeon Phi boards with HBM had a few modes of operation. The HBM could act as a cache for main memory, or you could set it up as directly addressable. You could then allocate buffers in that address space and know they'd never be evicted. I wonder if it was ever useful though. If you're able to make your algorithms stay within a certain block of memory, just allocating that in main memory and letting the cache do its job would seem to achieve the same goal. I've heard that a frequent complaint with the Phi was that the speedups were absolutely real after code was modified to suit the architecture, but then when the adjusted code was tested on conventional Xeons it was sped up almost as much.
- bjoli 4y agoIt is 96 mb per CCD, which will probably impose limitations. But it still tickles my imagination :)