It's so they don't have to change the topology from the ring bus in the consumer parts while boosting the effective core count. Look at a 12900K block diagram.

It's so they don't have to change the topology from the ring bus in the consumer parts while boosting the effective core count. Look at a 12900K block diagram. Four efficiency cores plus their combined L2 take up the same amount of die area as a P core. This means they don't have to deal with mesh interconnects or something like Infinity Fabric (which they already tried on Ivy Bridge-EP and were sorely dissatisfied with) and kick the can further down the road.