I am guessing here, but these boards seem to be geared towards accelerated data transfers to feed GPUs. Some GPU cluster workloads are limited by node to node d

I am guessing here, but these boards seem to be geared towards accelerated data transfers to feed GPUs. Some GPU cluster workloads are limited by node to node data transfers that need to go through several slow bus transfers between GPUs in different nodes with traditional computer architectures. These DPUs are spec'ed to act as a kind of programmable beefy DMA controller bridging directly between GPUs and some fast interconnect and storage.