If you scale frequency down far enough then leakage power can easily dominate, and a decade ago it was bad enough that race-to-idle really was more power effici

If you scale frequency down far enough then leakage power can easily dominate, and a decade ago it was bad enough that race-to-idle really was more power efficient than the DVFS most SoCs could do. Vendors were so bad at this that one of ARM's largest motivations for big.LITTLE so that their partners could have any semblance of DVFS that actually saved power at lower perf states. Although, I think the blogger only measures pinning on different CPUs, not the effect of DVFS vs. race-to-idle, so his statement is a non sequitur. Because of course a power-optimized arch is going to be more efficient than a perf-optimized arch (modulo uncore power), and that's been known and true since forever.