3 ms·

> Conventional wisdom, at least for SMP chips, is that this is the most efficient strategy, as it gets the task out of the way as quickly as possible. I've hea

> Conventional wisdom, at least for SMP chips, is that this is the most efficient strategy, as it gets the task out of the way as quickly as possible. I've heard this conventional wisdom cited repeatedly in the realm of embedded devices, but I don't have any idea how it could possibly be true: in a synchronous CMOS chip, power scales with the square of voltage, and in order to push the chip to higher frequencies, you have to increase the (gate? rail?) voltage - doesn't that mean that computing things at lower frequencies is almost always more efficient?

wmf 5y ago
It depends on the idle power.
brigade 5y ago
If you scale frequency down far enough then leakage power can easily dominate, and a decade ago it was bad enough that race-to-idle really was more power efficient than the DVFS most SoCs could do. Vendors were so bad at this that one of ARM's largest motivations for big.LITTLE so that their partners could have any semblance of DVFS that actually saved power at lower perf states. Although, I think the blogger only measures pinning on different CPUs, not the effect of DVFS vs. race-to-idle, so his statement is a non sequitur. Because of course a power-optimized arch is going to be more efficient than a perf-optimized arch (modulo uncore power), and that's been known and true since forever.
nagisa 5y ago
Running a core doesn't only run the core itself. There is a fair amount of supporting circuits including, but not limited to, things like memory controller, I/O bus, peripherals, etc. These can sip a non-trivial amount of power, and if a task running on an efficiency core kept them all up, you ultimately might end up with greater aggregate power use. Nowadays in modern chips these other circuits seem to be brought down to the low power states much more aggressively.

3 ms·

> Conventional wisdom, at least for SMP chips, is that this is the most efficient strategy, as it gets the task out of the way as quickly as possible. I've hea

by throw10920 5y ago

wmf 5y ago
It depends on the idle power.
brigade 5y ago
If you scale frequency down far enough then leakage power can easily dominate, and a decade ago it was bad enough that race-to-idle really was more power efficient than the DVFS most SoCs could do. Vendors were so bad at this that one of ARM's largest motivations for big.LITTLE so that their partners could have any semblance of DVFS that actually saved power at lower perf states. Although, I think the blogger only measures pinning on different CPUs, not the effect of DVFS vs. race-to-idle, so his statement is a non sequitur. Because of course a power-optimized arch is going to be more efficient than a perf-optimized arch (modulo uncore power), and that's been known and true since forever.
nagisa 5y ago
Running a core doesn't only run the core itself. There is a fair amount of supporting circuits including, but not limited to, things like memory controller, I/O bus, peripherals, etc. These can sip a non-trivial amount of power, and if a task running on an efficiency core kept them all up, you ultimately might end up with greater aggregate power use. Nowadays in modern chips these other circuits seem to be brought down to the low power states much more aggressively.