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These Apple Silicon chips are already very efficient, so it is pleasantly surprising to see the ability to reduce power consumption by 66%. I am wondering thou
by Kon-Peki 5y ago
These Apple Silicon chips are already very efficient, so it is pleasantly surprising to see the ability to reduce power consumption by 66%. I am wondering though - with some tasks it may be possible to implement using multiple algorithms/approaches, and that could make the differences even larger (if I am pinning to E cores, use algorithm A for maximum efficiency but if I am using P+E cores, use algorithm B for maximum performance).
- wmf 5y agouse algorithm A for maximum efficiency but use algorithm B for maximum performance This is pretty rare; the fastest algorithm is almost always the most efficient.
- Lichtso 5y agoFor purely sequential algorithms I agree, fewer work steps means less energy used and less time spent. But the picture is very different when it comes to parallel algorithms. There often is a tradeoff between doing more redundant work to reduce the latency and finish faster overall at the expense of more energy being used. One example is the "scan" operation on GPUs. There are lots of different algorithms to do it which form a gradient between fast and efficient. For reference see page 2 of this paper: https://research.nvidia.com/publication/2016-03_single-pass-parallel-prefix-scan-decoupled-look-back https://research.nvidia.com/publication/2016-03_single-pass-...