More fine-grained. Because separate cores each have their own cache, and their own program counter, there's a lot of communication overhead between them. When

More fine-grained. Because separate cores each have their own cache, and their own program counter, there's a lot of communication overhead between them. When you're using instruction-level parallelism[1], you can actually do stuff like "perform a single add and a single multiply in parallel, then add them together", and the system is designed so that you aren't adding any overhead when you do that. [1]: MIMD instructions are one way of doing this, but the computer you're reading HN on is probably an out-of-order superscalar, which accomplishes the same thing implicitly.