On its last iteration of cores, SiFive had shrunk the gap to being only within 2 years of ARM's best processors. Yet catching up simply couldn't be done before

On its last iteration of cores, SiFive had shrunk the gap to being only within 2 years of ARM's best processors. Yet catching up simply couldn't be done before because RISC-V was lacking functionality. As of December's 15 new ratified extensions, this is no longer the case. Several companies are currently working on high performance implementations. One of them is Tenstorrent, where there's a team led by Jim Keller working on this. It is supposed to enter the market near the end of this year. I do suspect it is going to take less than 5 years to see RISC-V take the performance crown.