Nit: you shouldn’t use RISC as a shorthand for RISC-V. The former is a well-known term. Yes, RISC-V is an open ISA, yes, like ARM there is no fab making canoni

Nit: you shouldn’t use RISC as a shorthand for RISC-V. The former is a well-known term. Yes, RISC-V is an open ISA, yes, like ARM there is no fab making canonical RISC-V chips. It does at least have the benefit of having support in the UEFI spec pretty much right out of the gate, which offers a standard boot path of sorts (Arm64 also supports UEFI, but most devices to this day have their own bespoke boot firmware and protocols, AFAIK. The unifying factor tends to be something like uboot, again, AFAIK.) but it also has more flexibility, which has the knock-on effect that it may be harder to know which RISC-V software can run on which RISC-V hardware. I’m very curious to see where it goes. As a tinkerer I definitely have been looking for entire desktop computers that, weak or not, are truly open source and documented from the ground up. RISC-V platforms don’t solve that entirely (in fact it’s probably the remainder of SoC IP that poses the biggest problems) but it does offer an interesting option for a CPU.