3 ms·
except it is not full end to end ECC, only inside the chips so they can get away with higher internal bit error rates (much like SSDs). "Enterprise" systems wi
by Andys 4y ago
except it is not full end to end ECC, only inside the chips so they can get away with higher internal bit error rates (much like SSDs).
"Enterprise" systems will continue to need additional ECC handling with motherboards and chipsets that support error correction over the transport of the data between memory and CPU.
Detecting bit flips (due to cosmic rays etc) inside the RAM is still a great thing and its great it will be available to everyone, but in the end, as densities continue to increase, the consumer may be still be presented with a similar bit error rate to before.