Fundamentally they are the same SMT concept though: multiple hardware threads that have separate register (and other) state but share an execution unit. HT as

Fundamentally they are the same SMT concept though: multiple hardware threads that have separate register (and other) state but share an execution unit. HT as an implementation tries to give long sequential execution windows to a hardware thread, it's designed to hide occasional long latencies (IO typically), but pays by having a higher switching cost. A barrel processor trades off individual instruction latency for a higher degree of parallelism and improved latency hiding.