That's right, I already do annotate my signals that way. It doesn't bother me as I know doing this will ensure connections can be validated at the block diagram

That's right, I already do annotate my signals that way. It doesn't bother me as I know doing this will ensure connections can be validated at the block diagram level. Clock and reset domains will be correct, interfaces that are incompatible cannot comnect. It's clear you have been burned, but I'm genuinely curious as to how. I've always found it to be smooth, and you can write a tcl representation of your bd for safe keeping, and what is generated is very readable (write_bd_tcl)