Well suppose you want your code to connect with IPI interfaces from Xilinx IP. You end up having to annotate it with magic attributes like this: (* X_INTE

Well suppose you want your code to connect with IPI interfaces from Xilinx IP. You end up having to annotate it with magic attributes like this: (* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 clk CLK" *) (* X_INTERFACE_PARAMETER = "ASSOCIATED_BUSIF disp1_tpg_axis:disp2_tpg_axis:ar_tpg_axis:artx0_axis:arrx0_axis:scaletx0_axis:tmrx0_axis:scaler, ASSOCIATED_RESET reset_l, FREQ_HZ 199980011" *) input clk; (* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 reset_l RST" *) (* X_INTERFACE_PARAMETER = "POLARITY ACTIVE_LOW" *) input reset_l; (* X_INTERFACE_INFO = "xilinx.com:interface:rx_mipi_ppi_if:1.0 cam0_rx_dphy DL3_RXDATAHS" *) input [7:0] cam0_rx_dphy_dl3_rxdatahs; It's horrible. Trust me, you will not like when things go wrong in larger block designs.