6 ms·
The block diagram is optional, everything can be done in Verilog. That said, I use IPI and find it very productive. Module reference flow lets you wrap Verilog
by tails4e 4y ago
The block diagram is optional, everything can be done in Verilog. That said, I use IPI and find it very productive. Module reference flow lets you wrap Verilog modules and expose IO as interfaces so composing a top level in the block diagram and hooking everything up is easy.
- orbifold 4y agoIt is optional but the alternative is also a pain to figure out and setup.
- tails4e 4y agoI completely agree, and I use IPI myself as I find it adds more than it costs, I was just pointing out its not mandatory as OP was not a fan
- jhallenworld 4y agoWell suppose you want your code to connect with IPI interfaces from Xilinx IP. You end up having to annotate it with magic attributes like this: (* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 clk CLK" *) (* X_INTERFACE_PARAMETER = "ASSOCIATED_BUSIF disp1_tpg_axis:disp2_tpg_axis:ar_tpg_axis:artx0_axis:arrx0_axis:scaletx0_axis:tmrx0_axis:scaler, ASSOCIATED_RESET reset_l, FREQ_HZ 199980011" *) input clk; (* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 reset_l RST" *) (* X_INTERFACE_PARAMETER = "POLARITY ACTIVE_LOW" *) input reset_l; (* X_INTERFACE_INFO = "xilinx.com:interface:rx_mipi_ppi_if:1.0 cam0_rx_dphy DL3_RXDATAHS" *) input [7:0] cam0_rx_dphy_dl3_rxdatahs; It's horrible. Trust me, you will not like when things go wrong in larger block designs.
- tails4e 4y agoThat's right, I already do annotate my signals that way. It doesn't bother me as I know doing this will ensure connections can be validated at the block diagram level. Clock and reset domains will be correct, interfaces that are incompatible cannot comnect. It's clear you have been burned, but I'm genuinely curious as to how. I've always found it to be smooth, and you can write a tcl representation of your bd for safe keeping, and what is generated is very readable (write_bd_tcl)