Really highlights the absolutely massive gap between Apple Silicon and Cortex/the-rest-of-ARM. Although you'd really want to classify which Cortex SoCs you're u

Really highlights the absolutely massive gap between Apple Silicon and Cortex/the-rest-of-ARM. Although you'd really want to classify which Cortex SoCs you're using in that list, as implementers love to chop off the L2 & L3 caches to save die space. This is how we ended up with the bigger.big.little configurations - the "biggest" CPU is just the full CPU with all the caches it was supposed to have had.