4 ms·

Eh, it's overstated. Classic CISC tended towards microcode because it allowed complex operations in way that didn't consume main data memory bandwidth. RISC i

Eh, it's overstated. Classic CISC tended towards microcode because it allowed complex operations in way that didn't consume main data memory bandwidth. RISC in a lot of ways was the recognition that when you can assume ubiquitous instruction caches for your ISA you can let your ASM writers just write what was microcode previously. Hot loops will be cached and out of the way of data bandwidth, but now there's no arbitrary limits to microcode program size. So RISC was a revolution over CISC, but CISC arguably always had 'a RISC core' inside, even before RISC was a thing.

zozbot234 5y ago
RISC does not resemble microcode all that much, VLIW is a lot closer to the mark. VLIW is also heavily μarch-dependent, much like microcode.
- monocasa 5y ago
  There's two kinds of microcode, vertical and horizontal. RISC resembles vertical microcode that can expand to horizontal microcode looking uops in a single decode stage. Having coded all three (vertical ucode, horizontal ucode, and RISC decode stage HDL) the biggest difference I've found is that RISC tends to be three address, and CISC vertical microcode to be two address. I think that comes from the same place as assuming the presence of an I$. The gate count niche that lets you have a large SRAM block for cache also let's lets you have a large SRAM block for your register file. You're therefore not as dependent on a single accumulator or two tightly coupled with your ALU like earlier CISC designs had to encourage.
  - zozbot234 5y ago
    Three-address designs trade off a larger insn word for fewer MOV insns and a more straightforward use of the register file. ("Compressed" insns are often two-reg special cases of a three-reg insn.) It's true that RISC tends to feature a higher amount of fully-general registers (as opposed to e.g. separate "data" and "address" registers) but that seems to be a separate development, possibly relating to the load-store approach.
    - monocasa 5y ago
      They're all related. When you have an accumulator based design with your ALU and registers, that necessitates a two address format. Or else you're not accumulating. If you don't have space next to your ALU except for one register, you're stuck with an accumulator.
ajross 5y ago
I'd argue the causality goes the other way. Microcode allows you to do complex things on top of a very minimal execution engine. You might use the same ALU for an add as you would for a multistage multiply as you would for a computed jump, etc... But as CPUs got bigger and suddenly had enough hardware to do "everything" at once, they had the problem of circuit depth. Sure, you can execute the whole instruction in one cycle but it's a really LONG cycle. You fix that problem with pipelining ([R]eally [I]nvented by [S]eymore [C]ray, of course). But you can't pipeline a complicated microcoded instruction set. Everything that happens has to fit in the same pipeline stages. So, the instruction set naturally becomes "reduced". Basically: RISC is the natural choice once VLIW gets rolling. It's not about simplification at all, it's about exploiting all the transistors on much more "complicated" chips.
- monocasa 5y ago
  Except older CPUs already sequenced heavily within an instruction. Even more than you might think. Z80 for instance only had a 4bit ALU and would pump it many times to get the bit width required. Early 808x would be 5 or so cycles per instruction on average. Internally though, their microcode issued once a cycle typically. > But you can't pipeline a complicated microcoded instruction set. Everything that happens has to fit in the same pipeline stages. So, the instruction set naturally becomes "reduced". That's what they said in the early 80s, but then the 486 came out. AFAIK the longest pipelined general purpose systems were also fairly heavily microcoded (Netburst).
  - ajross 5y ago
    The 80486 was only minimally pipelined, and in fact if you squint it fits what would later become the standard model: where an "expansion" engine at the decode level emits code for the later stages (which look more like a RISC pipeline with separated cache/execute/commit stages). That engine is still microcoded (because VLIW might have been rolling but no way can you do a uOp cache in 2M transistors), and still limited to multicycle instruction execution for all but the simplest forms. Basically, if you were handed the transistor budget of an 80486 and told to design an ISA, you'd never have picked a microcoded architecture with a bunch of addressing modes. People who did RISC in those chip sizes (MIPS R4000, say) were beating Intel by 2-3x on routine benchmarks. Again: it was the budget that informed the choice. Chips were bigger and people had to figure out how to make 2M transistors work in tandem. And obviously when chips got MUCH bigger it stopped being a problem because dynamic ISA conversion becomes an obvious choice when you have 200M transistors.

zozbot234 5y ago

RISC does not resemble microcode all that much, VLIW is a lot closer to the mark. VLIW is also heavily μarch-dependent, much like microcode.

monocasa 5y ago
There's two kinds of microcode, vertical and horizontal. RISC resembles vertical microcode that can expand to horizontal microcode looking uops in a single decode stage. Having coded all three (vertical ucode, horizontal ucode, and RISC decode stage HDL) the biggest difference I've found is that RISC tends to be three address, and CISC vertical microcode to be two address. I think that comes from the same place as assuming the presence of an I$. The gate count niche that lets you have a large SRAM block for cache also let's lets you have a large SRAM block for your register file. You're therefore not as dependent on a single accumulator or two tightly coupled with your ALU like earlier CISC designs had to encourage.
- zozbot234 5y ago
  Three-address designs trade off a larger insn word for fewer MOV insns and a more straightforward use of the register file. ("Compressed" insns are often two-reg special cases of a three-reg insn.) It's true that RISC tends to feature a higher amount of fully-general registers (as opposed to e.g. separate "data" and "address" registers) but that seems to be a separate development, possibly relating to the load-store approach.
  - monocasa 5y ago
    They're all related. When you have an accumulator based design with your ALU and registers, that necessitates a two address format. Or else you're not accumulating. If you don't have space next to your ALU except for one register, you're stuck with an accumulator.

ajross 5y ago

I'd argue the causality goes the other way. Microcode allows you to do complex things on top of a very minimal execution engine. You might use the same ALU for an add as you would for a multistage multiply as you would for a computed jump, etc... But as CPUs got bigger and suddenly had enough hardware to do "everything" at once, they had the problem of circuit depth. Sure, you can execute the whole instruction in one cycle but it's a really LONG cycle. You fix that problem with pipelining ([R]eally [I]nvented by [S]eymore [C]ray, of course). But you can't pipeline a complicated microcoded instruction set. Everything that happens has to fit in the same pipeline stages. So, the instruction set naturally becomes "reduced". Basically: RISC is the natural choice once VLIW gets rolling. It's not about simplification at all, it's about exploiting all the transistors on much more "complicated" chips.

monocasa 5y ago
Except older CPUs already sequenced heavily within an instruction. Even more than you might think. Z80 for instance only had a 4bit ALU and would pump it many times to get the bit width required. Early 808x would be 5 or so cycles per instruction on average. Internally though, their microcode issued once a cycle typically. > But you can't pipeline a complicated microcoded instruction set. Everything that happens has to fit in the same pipeline stages. So, the instruction set naturally becomes "reduced". That's what they said in the early 80s, but then the 486 came out. AFAIK the longest pipelined general purpose systems were also fairly heavily microcoded (Netburst).
- ajross 5y ago
  The 80486 was only minimally pipelined, and in fact if you squint it fits what would later become the standard model: where an "expansion" engine at the decode level emits code for the later stages (which look more like a RISC pipeline with separated cache/execute/commit stages). That engine is still microcoded (because VLIW might have been rolling but no way can you do a uOp cache in 2M transistors), and still limited to multicycle instruction execution for all but the simplest forms. Basically, if you were handed the transistor budget of an 80486 and told to design an ISA, you'd never have picked a microcoded architecture with a bunch of addressing modes. People who did RISC in those chip sizes (MIPS R4000, say) were beating Intel by 2-3x on routine benchmarks. Again: it was the budget that informed the choice. Chips were bigger and people had to figure out how to make 2M transistors work in tandem. And obviously when chips got MUCH bigger it stopped being a problem because dynamic ISA conversion becomes an obvious choice when you have 200M transistors.