3 ms·
Are you sure? TLB misses mean a pagewalk. Sure, the directory tree is probably in L3 cache, but repeatedly pagewalking through L3 to find a memory address is go
by dragontamer 5y ago
Are you sure? TLB misses mean a pagewalk. Sure, the directory tree is probably in L3 cache, but repeatedly pagewalking through L3 to find a memory address is going to be slower than just fetching it from the in core TLB.
I know that modern cores have dedicated page walking units these days, but I admit that I've never tested the speed of them.
- seoaeu 5y agoIt only takes ~200KB to store page tables for 96MB of address space. So the page table entries might mostly stay in the L1 and L2 caches
- dragontamer 5y agoI think you made an error in your assumptions. Each 64byte cache line could feasibly come from a different page in the worst case. I think modern processors actually pull 128 bytes from RAM at the L3 level, if each 128 L3 cache line is from a different page, that's 768k pages in the 96MB L3 cache. That being said, huge pages won't help much in this degenerate case. So your assumption might be valid for this argument actually. So maybe it's not that much of an error.
- seoaeu 5y agoMy estimate is for a small number of contiguous regions. It is true that if you adversarially construct a set of cache lines, you might need a far larger amount of memory to store page tables for them. Whether you consider that an "error" or just a simplifying assumption is a matter of opinion I suppose