3 ms·

> That's right, you run out of TLB-entries before you run out of L3 cache these days. This is more reasonable than it sounds. A TLB miss can in many cases be f

by seoaeu 5y ago

> That's right, you run out of TLB-entries before you run out of L3 cache these days. This is more reasonable than it sounds. A TLB miss can in many cases be faster than a L3 cache hit

jeffbee 5y ago
It's also misleading because it has 8 cores and each of them has 2048 l2 TLB entries. Altogether they can cover 64MiB of memory with small pages.
- dragontamer 5y ago
  But 5800x3D has 96MB of L3. So even if all 8 cores are independently working on different memory addresses, you still can't cover all 96MB of L3 with the TLB. EDIT: Well, unless you use 2MB hugepages of course.
  - jeffbee 5y ago
    That's another thing which is recent. Before Haswell, x86 cores had almost no huge TLB entries. IvyBridge only had 32 in 2MiB mode, compared to 64 + 512 in 4KiB mode.
dragontamer 5y ago
Are you sure? TLB misses mean a pagewalk. Sure, the directory tree is probably in L3 cache, but repeatedly pagewalking through L3 to find a memory address is going to be slower than just fetching it from the in core TLB. I know that modern cores have dedicated page walking units these days, but I admit that I've never tested the speed of them.
- seoaeu 5y ago
  It only takes ~200KB to store page tables for 96MB of address space. So the page table entries might mostly stay in the L1 and L2 caches
  - dragontamer 5y ago
    I think you made an error in your assumptions. Each 64byte cache line could feasibly come from a different page in the worst case. I think modern processors actually pull 128 bytes from RAM at the L3 level, if each 128 L3 cache line is from a different page, that's 768k pages in the 96MB L3 cache. That being said, huge pages won't help much in this degenerate case. So your assumption might be valid for this argument actually. So maybe it's not that much of an error.
    - seoaeu 5y ago
      My estimate is for a small number of contiguous regions. It is true that if you adversarially construct a set of cache lines, you might need a far larger amount of memory to store page tables for them. Whether you consider that an "error" or just a simplifying assumption is a matter of opinion I suppose

by seoaeu 5y ago

> That's right, you run out of TLB-entries before you run out of L3 cache these days. This is more reasonable than it sounds. A TLB miss can in many cases be faster than a L3 cache hit

jeffbee 5y ago

It's also misleading because it has 8 cores and each of them has 2048 l2 TLB entries. Altogether they can cover 64MiB of memory with small pages.

dragontamer 5y ago
But 5800x3D has 96MB of L3. So even if all 8 cores are independently working on different memory addresses, you still can't cover all 96MB of L3 with the TLB. EDIT: Well, unless you use 2MB hugepages of course.
- jeffbee 5y ago
  That's another thing which is recent. Before Haswell, x86 cores had almost no huge TLB entries. IvyBridge only had 32 in 2MiB mode, compared to 64 + 512 in 4KiB mode.

dragontamer 5y ago

Are you sure? TLB misses mean a pagewalk. Sure, the directory tree is probably in L3 cache, but repeatedly pagewalking through L3 to find a memory address is going to be slower than just fetching it from the in core TLB. I know that modern cores have dedicated page walking units these days, but I admit that I've never tested the speed of them.

seoaeu 5y ago
It only takes ~200KB to store page tables for 96MB of address space. So the page table entries might mostly stay in the L1 and L2 caches
- dragontamer 5y ago
  I think you made an error in your assumptions. Each 64byte cache line could feasibly come from a different page in the worst case. I think modern processors actually pull 128 bytes from RAM at the L3 level, if each 128 L3 cache line is from a different page, that's 768k pages in the 96MB L3 cache. That being said, huge pages won't help much in this degenerate case. So your assumption might be valid for this argument actually. So maybe it's not that much of an error.
  - seoaeu 5y ago
    My estimate is for a small number of contiguous regions. It is true that if you adversarially construct a set of cache lines, you might need a far larger amount of memory to store page tables for them. Whether you consider that an "error" or just a simplifying assumption is a matter of opinion I suppose