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Story time! 28 years ago, I worked for Mietec, a company that had a fab that is now owned by OnSemi. The mask preparation team told me the following: One tim
by tverbeure 5y ago
Story time!
28 years ago, I worked for Mietec, a company that had a fab that is now owned by OnSemi.
The mask preparation team told me the following:
One time they received the GDS2 file with the mask layers (that’s the golden file that gets created when you do a tape-out) from a customer, did their usual preparation and design rule checks, and sent it to the mask maker.
A few days later, they received an email stating that they couldn’t process the file due to “the presence of twitty birds and Christmas trees.” And, indeed, upon closer inspection, the design contained these elements.
However the metal vias to make those images were only on one layer, and not connected to others.
The resulting issue was one of “floating vias”. (That’s the exact wording that I remember all these years later, but Google doesn’t turn up anything.) For some reason, these unconnected vias couldn’t be held in place during some steps of either the mask masking process or the actual silicon production step, and that’s why the mask maker rejected it.
A new guideline was issued by my company that designs should not have these kind of graphic elements and logos to avoid wasting engineering resources on something frivolous.
What I don’t understand is why this issue wasn’t detected during design rule checking at the customer’s site or at our mask making preparation stage. But that’s a different story.
Either way: I’ve worked on a lot of chips and for a bunch of different companies, and I’m not aware of there being any graphical elements in them either. Masks were moderately expensive 28 years ago (something like $25k), they’re insanely expensive today (millions.) You don’t want to risk anything…
- jjoonathan 5y agoI've been out of touch for a while -- what's the driving factor in mask expense these days? Time in the mask writer? Something about only being able to pack so many simultaneous electron beams next to each other before they fuzz out?
- tverbeure 5y agoI can't offer you any more insights other than "it's expensive to make things that are just a few nanometer in size..."
- stormbrew 5y agoIt's really wild to me that there isn't a market out there for smaller chip manufacturers at larger feature scales to still do production orders in that price range or cheaper even. Or, if there are, they're hard to find and get access to. Lots of chips in use today are still not anywhere near the tiny end of the scale, and they're clearly still being manufactured somewhere, but it's like economies of scale have somehow worked against price in IC manufacturing in some ways (but obviously not others: per-feature-count is obviously much more cost effective now).
- tverbeure 5y agoThese older fabs still exist and are now used for specialty processes and products: sensors, high voltage electronics etc. They are useless for anything digital: even an FPGA is more cost effective, which is saying something…
- jecel 5y agoJust adding processing steps requires more masks. Moving from visible light to smaller wavelengths requires more and more sophisticated materials for the masks with smaller and smaller imperfections. To push a technology like DUV (deep ultra violet) further and further requires multi-patterning, which means several masks for a single processing step. For EUV (extreme ultra violet) no material is transparent so the masks are actually mirrors. With 40 alternating silicon and molybdenum layers, each the exact thickness to match the 13.5nm wavelength, you can reflect enough of the EUV beam to get the job done. Making such a mask is a lot more expensive than one that is basically a glass photographic plate. The time to actually write a mask has gone up by a large factor, as you mentioned. The combination of all the factors increases the cost of the masks from a few thousand dollars for 1970s technology to many millions today.
- userbinator 5y agoFor some reason, these unconnected vias couldn’t be held in place during some steps of either the mask masking process or the actual silicon production step, and that’s why the mask maker rejected it. They can cause damage due to static accumulation during the processing steps. It's hard to find good references to this due to the secretive nature of IC manufacturing in general, but here's some discussion: https://www.edaboard.com/threads/question-about-metal-filling.30432/ https://www.edaboard.com/threads/question-about-metal-fillin...