4 ms·

I might be missing something, but I never figured out where mill was saving all those gates they claimed. It could be my lack of imagination, but the straightf

I might be missing something, but I never figured out where mill was saving all those gates they claimed. It could be my lack of imagination, but the straightforward way to implement the belt just looks like a ROB and bypass network just like a normal OoO core spends it's gates on. And on the frontend, sure they mark instruction boundaries within an instruction bundle, but you still need N barrel shifters (where N is the number of max instructions per cycle) to get at them, and that's the expensive part of wide decode. Even 16bit aligned is so much nicer for the critical path than 8-bit, bit aligned is absolutely crazy town.

pjc50 5y ago
Bit aligned instructions? Yeah, that definitely sounds mad, like my joke proposal that instructions should be Huffman-coded so the frequent ones take fewer bits. Might make sense if you're doing a microcontroller with a few K of ROM and need to save bits, but otherwise no.
- AnimalMuppet 5y ago
  I'm not sure that you'd do that even on a microcontroller. If you don't have the ROM space, you probably also don't have the transistor budget for the decoder you'd need to handle that.
pclmulqdq 5y ago
I think they are claiming a savings on a register file, which is not nothing, but not exactly a ton. Also they save on register renaming and scoreboards, which have some gate count. The biggest thing that they seem to have is that they can compute an enormous number of instructions per cycle without blowing up the size of the bypass network.
- colejohnson66 5y ago
  If their goal is to save on register file space, they're barking up the wrong tree, IMO. The Skylake-X die[0], for example, dedicates only about 1% to the integer register file, and only about 2.5% for the floating point register file. The decoder and scheduler also take up only single digit percents. Granted, this is a top of the line superscalar processor with AVX-512 and megabytes of cache, but my point still stands. The vast majority of the gates are in everything else: cache, execution units, branch prediction, load/store, die interfaces, etc. [0]: https://twitter.com/GPUsAreMagic/status/1256866465577394181 https://twitter.com/GPUsAreMagic/status/1256866465577394181

pjc50 5y ago

Bit aligned instructions? Yeah, that definitely sounds mad, like my joke proposal that instructions should be Huffman-coded so the frequent ones take fewer bits. Might make sense if you're doing a microcontroller with a few K of ROM and need to save bits, but otherwise no.

AnimalMuppet 5y ago
I'm not sure that you'd do that even on a microcontroller. If you don't have the ROM space, you probably also don't have the transistor budget for the decoder you'd need to handle that.

pclmulqdq 5y ago

I think they are claiming a savings on a register file, which is not nothing, but not exactly a ton. Also they save on register renaming and scoreboards, which have some gate count. The biggest thing that they seem to have is that they can compute an enormous number of instructions per cycle without blowing up the size of the bypass network.

colejohnson66 5y ago
If their goal is to save on register file space, they're barking up the wrong tree, IMO. The Skylake-X die[0], for example, dedicates only about 1% to the integer register file, and only about 2.5% for the floating point register file. The decoder and scheduler also take up only single digit percents. Granted, this is a top of the line superscalar processor with AVX-512 and megabytes of cache, but my point still stands. The vast majority of the gates are in everything else: cache, execution units, branch prediction, load/store, die interfaces, etc. [0]: https://twitter.com/GPUsAreMagic/status/1256866465577394181 https://twitter.com/GPUsAreMagic/status/1256866465577394181