>it's really tough choosing component values that don't ring like a bell, a loud bell, at pretty high frequencies That doesn't sound right to me. It's not real

>it's really tough choosing component values that don't ring like a bell, a loud bell, at pretty high frequencies That doesn't sound right to me. It's not really about the component values. It's about the parasitics and the edge rates that can ring those parasitics. The main LC elements are not usually the problem (especially at high frequencies). > for simulations You cannot simulate any SMPS for EMC reasons without including the layout. Full stop, do not pass Go, etc. You can simulate for functionality and you can avoid some well-known traps, but you'll never be able to be confident without the layout included. Never. > run the input voltage as high as feasable Usually you want your duty cycle around 50%. Higher input voltages will push that down, which is usually a bad thing and requires special measures to compensate. And switch capacitances are rarely a major problem below line voltages, so you don't get much return on it either. What, exactly, are you trying to do? (Disclaimer: professional EE but not a power guy. I do little SMPS stuff up to 24V all the time though, especially low-noise analog supplies.)