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ARM ISA has probably little to do with the efficiency, although: * the memory model is slightly more relaxed * instruction decoding is obviously simpler, and

by temac 4y ago

ARM ISA has probably little to do with the efficiency, although: * the memory model is slightly more relaxed * instruction decoding is obviously simpler, and while the impact of x86 decoding was not that major at a point, I suspect it has increased with time What matters is mostly the microarchitecture of Apple, and, yes, the 5nm. IIRC at the beginning of the Zen projet, AMD wanted to do 2 versions: 1 with an x86 frontend, and one with an ARM one. They would probably have had very similar performance profiles, and I suspect at most a dozen percent of diff for energy consumption. Intel is currently very far from that to reach a core perf similar to the one of the M1.

ClumsyPilot 4y ago
> the impact of x86 decoding was not that major at a point, I suspect it has increased with time Can you elaborate why decode would become more problematic over time?
- vlovich123 4y ago
  if I recall correctly ARM instructions are fixed length. You can start deciding instructions on parallel at the same time (ie right after you fetch). X86 uses variable length instructions. Decoding the next instruction requires the previous one to be decoded (think decompression vs reading fixed records). Hopefully I got that right. Now in theory Intel and AMD do employ tricks to optimize x86 decode. If I recall this correctly, they decide opportunistically several possible paths simultaneously and start speculatively executing the ones that turn out to be valid instructions. Likely this works pretty well (+ the variable length means better utilization of the code cache).
klelatti 4y ago
Not disagreeing with your core point on the architectures but there are a few other areas of possible advantage: - No 32 bit support - Fewer other legacy ISA features to support - big.LITTLE style efficiency/ performance cores (until latest generation Intel) On the first two fewer transistors wasted mean more to spend elsewhere (eg on caches).

by temac 4y ago

ClumsyPilot 4y ago

> the impact of x86 decoding was not that major at a point, I suspect it has increased with time Can you elaborate why decode would become more problematic over time?

vlovich123 4y ago
if I recall correctly ARM instructions are fixed length. You can start deciding instructions on parallel at the same time (ie right after you fetch). X86 uses variable length instructions. Decoding the next instruction requires the previous one to be decoded (think decompression vs reading fixed records). Hopefully I got that right. Now in theory Intel and AMD do employ tricks to optimize x86 decode. If I recall this correctly, they decide opportunistically several possible paths simultaneously and start speculatively executing the ones that turn out to be valid instructions. Likely this works pretty well (+ the variable length means better utilization of the code cache).

klelatti 4y ago

Not disagreeing with your core point on the architectures but there are a few other areas of possible advantage: - No 32 bit support - Fewer other legacy ISA features to support - big.LITTLE style efficiency/ performance cores (until latest generation Intel) On the first two fewer transistors wasted mean more to spend elsewhere (eg on caches).