3 ms·
It must be the coverable amount. At 16kB pages, it would be 2048 entries, a reasonable TLB size. The CPU is said to have 3072 L2TLB entries, so that's not quit
by ip26 5y ago
It must be the coverable amount. At 16kB pages, it would be 2048 entries, a reasonable TLB size.
The CPU is said to have 3072 L2TLB entries, so that's not quite a match. Perhaps this "32MB TLB" is a GPU-only TLB; perhaps it does not support variable page sizes.
- kimixa 5y agoBut the same limits are true on any GPU that does virtual memory - it's nothing special about that and doesn't interact really with the TBDR vs Immediate rendering the thread seems to suggest. If anything, a TBDR implementation may put less pressure on the MMU TLB, as the tile buffer contents are statically allocated based on the pipeline so may not even have a backing mapping, while on an intermediate mode renderer would have to have an intermediate buffer somewhere for stuff like the color and depth values of an ongoing render, which is likely translated through the MMU. Which is why I believe they've confused the TLB (Translation Lookaside buffer of the MMU) with the Tile Buffer of a TBDR renderer (IE the on-chip working buffer for in-tile intermediate results of shading).