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MIPS provides highly scalable RISC processor IP
- johnklos 5y agoRight... Just what everyone wants: a "patent portfolio" intertwined with supposedly open architecture. BTW - it's somewhat telling that the company isn't even self-aware enough to run their own web site on MIPS.
- snvzz 5y agoIf they're RISC-V members, then they've signed the RISC-V agreement. It takes care of any potential patent issues.
- simne 5y agoLooks like Russians captured MIPS and defaced it :(
- yjftsjthsd-h 5y agoI know this is a kind of stupid little thing, but I really wish they'd rebranded more completely if they were going to do this. "That box has a MIPS processor in it. But not a MIPS processor, a MIPS RISC-V processor." We're going to end up with OSs list on their "supported platforms" page things like MIPS, MIPS64, MIPS-brand RISC-V.
- HideousKojima 5y agoARM has been doing basically the same thing for decades now with all the different sub versions of ARMv7, 8, 9 etc.
- yjftsjthsd-h 5y agoThose are versions of the same(ish) ISA and are (usually?) backwards compatible. I'd mind less if MIPS-the-company made CPUs that were RISC-V with a MIPS-the-ISA compatibility mode, or otherwise actually had continuity; it's the apparent plan to throw away the ISA but keep the name that's jarring.
- dragontamer 5y agoARM Cortex M0+ looks nothing like ARM v8. ARM Cortex M0+ has more similarities with the ATTiny84 / Arduino chips than with cellphone-sized ARMs.
- pajko 5y agoCortex M0+ is ARMv6-M. ARMv8 has also an M variant, Cortex M33 is ARMv8-M mainline. ARMv6-M and ARMv8-M have quite a lot of things in common, as v8 is a superset of v6. Or did you mean ARMv8-A? Well, ARMv8-A and ARMv8-M are not compatible intentionally, as the the A variant is strictly 64-bit (some implementations support AArch32 though) and the support for thumb instruction set has been dropped.
- GoblinSlayer 5y agoThat's reasonable: RISC-V is mostly a cleaned up MIPS, so can definitely go as a MIPS family ISA.
- pajko 5y agoMIPS is as cleaned up as needs to be. RISC-V removed important features and adds loads of bloats via extensions.
- gpderetta 5y agoRISC-V itself is a very confusing branding. "Not a MIPS RISC processor, a MIPS RISC-V processor!"
- dkersten 5y agoIts not really a "stupid little thing", it sounds like a big cause of confusion.
- jogu 5y agoTo be fair this isn't an announcement of a product or anything like that, so their line of RISC-V processors could have distinct branding e.g. FooBar RISC-V Processors (by MIPS). Totally agree though that they should probably be careful and put some thought into how they brand these.
- CalChris 5y agoThe title really should say RISC-V rather than RISC. MIPS already is a RISC, one of the first.
- ClumsyPilot 5y agoYeah, i couldn't work out whats happening at first
- MisterTea 5y agoMIPS is making RISC-V processors? What happened to the MIPS arch itself?
- my123 5y agoSlowly dithered away...
- unfocussed_mike 5y agoYep. Amazing when you consider that Windows CE ran on MIPS hardware (NEC VR3xxx and VR4xxx chips). Casio's Cassiopeia series for example. It's not quite a "what could have been" because they were really eclipsed by the StrongARM at that point, as I recall, but it's very notable how quickly people lost interest in MIPS.
- dboreham 5y agoWindowsNT ran on MIPS too.
- Nursie 5y agoThe PSP (Playstation Portable) was a MIPS device too. My last encounter with MIPS was a payment terminal I worked on in 2014, which sadly never made it to market. There was a company making 'secure' variants with a variety of hardware features suited to payment terminals - a hardware TRNG, a couple of pins which transmitted and received a TRNG signal constantly, so that you could attach a tamper-detection wire and brick the device if it broke, key-erasure features etc.
- lpmay 5y agoThe "PIC32" family from microchip is also MIPS based
- my123 5y agoIt lived on for quite a while with a strong position in the networking market later on. But then instead of focusing on networking/infrastructure hardware like they could have, they went on a wild goose chase... to try to gain a place in phones.
- Taniwha 5y agoSurely the headline should be "Berkeley beats Stanford"?
- jecel 5y agoIn terms of architectural style RISC-V is more similar to MIPS (via DLX) than to RISC-I, II, SOAR and SPUR (and Sparc).
- musicale 5y agoMIPS had their chance with MIPS Open and bungled it. If they hadn't, then there wouldn't have been the same need for RISC-V. It's a shame because MIPS had a perfectly usable architecture with 64-bit support and a well supported toolchain. It's sad to see it abandoned because it was historically one of the first successful RISC architectures that was used in everything from the DECstation to the PlayStation.
- yjftsjthsd-h 5y ago> MIPS had their chance with MIPS Open and bungled it. If they hadn't, then there wouldn't have been the same need for RISC-V. I would, someday, like to hear a history of how we did get to RISC-V being needed. MIPS never actually made it to being open source, but I thought SPARC[0] and POWER[1] both did make it, quite a long time ago now, j-core is a thing[2] although that may have happened too late, OpenRISC[3] is apparently decades old now but just... never went anywhere? I'm probably missing context, but it seems like we should have had at least 2 and possibly as many as 5 open source processor designs by the time RISC-V took off. And now it has taken off, and the ecosystem has latched onto it and it will almost certainly come to dominate, but I still don't understand why it was needed at all or why it succeeded when everything else failed. [0] https://en.wikipedia.org/wiki/OpenSPARC https://en.wikipedia.org/wiki/OpenSPARC [1] https://en.wikipedia.org/wiki/OpenPOWER_Foundation https://en.wikipedia.org/wiki/OpenPOWER_Foundation - possibly not actually FOSS like RISC-V; unclear to me whether IBM is just using "open" to mean "we share with other companies who are working with us" [2] "J-core is a clean-room open source processor and SOC design using the SuperH instruction set, implemented in VHDL and available royalty and patent free under a BSD license." https://j-core.org/ https://j-core.org/ [3] https://en.wikipedia.org/wiki/OpenRISC https://en.wikipedia.org/wiki/OpenRISC
- chasil 5y agoSPARC and MIPS have some architectural oddities that were designed for their original pipelines that make them awkward. https://www.jwhitham.org//2016/02/risc-instruction-sets-i-have-known-and.html https://www.jwhitham.org//2016/02/risc-instruction-sets-i-ha... https://news.ycombinator.com/item?id=11607119 https://news.ycombinator.com/item?id=11607119
- rbanffy 5y agoHyperscalers make it easier to launch a new ISA - instead of convincing a lot of manufacturers that build diverse products with it, all of which you need to more or less manage into compatibility so that your software doesn't get diluted, now you need to convince one or two hyperscalers that your solution will offer the same capacity in less space for less power. That, of course, after some compiler enablement, but that's something every ISA needs to do. You can start by building a beefy server chip instead of a full lineup from thin laptops all the way up to beefy servers.
- lizardactivist 5y agoI may recall wrong here, but I think MIPS is the only architecture in use that has one's complement integer arithmetics.
- yjftsjthsd-h 5y agoIf you wanted that, couldn't you make a RISC-V chip with a custom extension to add that as a handful of extra instructions?
- lizardactivist 5y agoNot sure, I'm not read up on RISC-V, but I don't know if someone would want it since AFAIK two's complement means fewer logic gates and a slimmer instruction set. One's complement arithmetics don't break in the few odd cases like two's complement do though, so there could be that.
- FullyFunctional 5y agoYou recall wrong.
- lizardactivist 5y agoEnlighten us then. If you're not too moody.
- FullyFunctional 5y agoNot much to say about it. Mips is twos compliment like all processors in the past ~60 years.
- azinman2 5y agoThe company is now Chinese owned, right? Would make sense they'd want to go for RISC-V now that MIPS itself isn't viable.