Sorta. Cache snooping has been part of the interconnect for years (it arguably is the interconnect), but this is about snooping cache line zeroing instructions

Sorta. Cache snooping has been part of the interconnect for years (it arguably is the interconnect), but this is about snooping cache line zeroing instructions without having to go out to memory as far as I understand it. So if a line is shared in two caches, it can be zeroed in both without getting the DRAM controller or even L3 involved.