4 ms·
...I think the actual patent is on moving the cache snooping into the interconnect? I think all of the figures presented are part of Intel's claim that any pro
by icegreentea2 5y ago
...I think the actual patent is on moving the cache snooping into the interconnect?
I think all of the figures presented are part of Intel's claim that any processor that implements cache snooping in the interconnect are subject to this patent.
- monocasa 5y agoSorta. Cache snooping has been part of the interconnect for years (it arguably is the interconnect), but this is about snooping cache line zeroing instructions without having to go out to memory as far as I understand it. So if a line is shared in two caches, it can be zeroed in both without getting the DRAM controller or even L3 involved.