Now imagine a large amount of memory connected to the cores through tiny metal wires on the chip itself. Now imagine that it's split into a bunch of small indep

Now imagine a large amount of memory connected to the cores through tiny metal wires on the chip itself. Now imagine that it's split into a bunch of small independent memories with enormous bandwidth, with data automatically migrating between them to cut down on wire delays. Give it a few years, and this could be reality.