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HP plans to release first memristor, alternative to flash and SSDs in 18 months
- jeroen 15y agoThe article mentions both 18 months and summer 2013. That's not entirely consistent.
- corin_ 15y agoIt's an estimate not an exact length of time. 18 months takes us to April 2013, so maybe they rounded April into "summer" or maybe they rounded 20 months to the nearest .5 of a year. Or maybe they class April as summer anyway. It's not like those two times are way different.
- Nicknameless 15y agoWell summer is December to February, so April is a fair way off... Perhaps they could do away with the stupid idea altogether and say 2nd quarter 2013 if they can't be more specific.
- themgt 15y agoThe specific quote was "We’re planning to put a replacement chip on the market to go up against flash within a year and a half" and "We have a lot of big plans for it and we're working with Hynix Semiconductor to launch a replacement for flash in the summer of 2013 and also to address the solid-state drive market" June 2013 is twenty months away, so "a year and a half" is a very reasonable approximation, which it looks like the article writers then approximated again as "18 months"
- aheilbut 15y agoWhatever happened with Nantero?
- dhughes 15y agoI doubt HP itself will exist in 18 months.
- bvi 15y agoHyperbole much?
- michaelcampbell 15y agoAll day, every day!
- leoc 15y agoEight days a wee-eeek!
- dhughes 15y agoI don't think that's possible, Jersey Shore doesn't have as much drama as HP.
- DasIch 15y agoEven if HP doesn't the technology for this will probably survive.
- viraptor 15y agoIt won't disappear. It could be split, close some sites, change leadership again, etc. but it won't simply cease to exist. The existing infrastructure itself is worth too much.
- zackattack 15y agoWhat would you say are HP's top 5 most valuable pieces of infrastructure?
- viraptor 15y agoJust guessing but: lab machines, buildings, purpose-built networks/processing centres, etc. I don't know how the production is organised, but assembly lines may be included.
- uniclaude 15y agoThis article is mostly made of quotes from an EEtimes article[1], adds no information or value to it, and is (to me at least) less readable. [1]:http://eetimes.com/electronics-news/4229171/HP-Hynix-to-launch-memristor-memory-2013?pageNumber=0 http://eetimes.com/electronics-news/4229171/HP-Hynix-to-laun...
- hornokplease 15y agoEE Times article submitted here: http://news.ycombinator.com/item?id=3080963 http://news.ycombinator.com/item?id=3080963
- modeless 15y agoAnd here: http://news.ycombinator.com/item?id=3081273 http://news.ycombinator.com/item?id=3081273
- pjscott 15y agoThe really exciting part here, to me, is the idea of fabricating large amounts of nonvolatile memory on top of a CPU. Modern processors already spend a huge amount of their time waiting on memory, and a great amount of power trying to hide that memory latency. If these guys can lower memory latency dramatically -- and it looks like they can -- computers would get a lot faster.
- TheEzEzz 15y agoThis would be a huge boon for scientific computing. The data is often huge, but all of it must be constantly pushed through the CPU every iteration.
- montecarl 15y agoAs the number of cores per socket is steadily increasing it is becoming more difficult to keep all of the cores on a single computer operating efficiently. A higher clock rate per core, or more cores per socket, is not very useful if they are all waiting on memory.
- rbanffy 15y agoUnless we are considering coupling lots of memory to the cores themselves, bypassing slow external buses.
- pjscott 15y agoNow imagine a large amount of memory connected to the cores through tiny metal wires on the chip itself. Now imagine that it's split into a bunch of small independent memories with enormous bandwidth, with data automatically migrating between them to cut down on wire delays. Give it a few years, and this could be reality.
- sliverstorm 15y agoNot if they continue cutting their hardware divisions, it won't.
- dmix 15y ago> Asked about the competition, Williams said: "Samsung has An even larger group working on this than we do." As a consumer, I'm indifferent to who does it. As long as it gets out.
- lordmatty 15y agoGreat to see some positive press on HP. Hope HP can innovate their way out of the current slump.
- plasma 15y agoWatch HP research's Stanley Williams describe the memristor and what they are working towards in more detail on YouTube: http://www.youtube.com/watch?v=bKGhvKyjgLY&sns=em http://www.youtube.com/watch?v=bKGhvKyjgLY&sns=em
- TheEzEzz 15y agoFrom the video: "So, I mean, we're all of a sudden talking petabits of memory in a square centimeter device. What can you do with that? Interesting to think about."
- bluehavana 15y agoThe no more hard drive and persistent ram thing should be really interesting. Completely change how we do things. Also, application specific processing... writing instruction sets for each application will be really interesting. Cell processing et al will be a thing of the past.
- georgemcbay 15y agoAll of those years spent trying to educate my family and non-technical friends on the difference between RAM and HDD and explaining how it is confusing when they tell me they couldn't install a program because their laptop was "out of memory".... wasted!
- speleding 15y agoI watched the whole 47 minutes of that talk on youtube, and it is actually really good. I have no qualifications in this field, but the talk is full of challenging ideas. You can skip reading the article.
- TheEzEzz 15y agoWhat are the implications for back end development? Will this greatly reduce server complexity (need for redundancy)? Could AWS just give you a machine in the cloud, and you wouldn't need to worry about databases and database backups and so on, you could just keep all your data locally in natural data structures?
- ericfrenkiel 15y agoThis would not necessarily affect back end development as you would still want high availability for the application by using an active-active setup across two availability zones in EC2. With regard to your question on data structures, yes - they would have to change. MySQL and most other databases use b-trees since they were meant to live on disk. Just running MySQL on memsistor-backed storage would result in a considerable waste of CPU and storage capacity (b-trees are not very compact). Running a database like MemSQL on memsistors would make the most sense since it uses data structures meant for DRAM.
- calebmpeterson 15y agoSo how would this affect what languages we use? How different data structures perform? etc. Will this amplify the end of the free lunch? I'm especially curious how Rich Hickey's approach to state, time, and identity in a functional language fit in?
- bane 15y agoEnlarge the data bus and...are we finally finding a way out of the von Neuman architecture?
- palish 15y agoIs the Von Neumann architecture related to the data bus?
- PurplePanda 15y agoIt operates by pushing data back and forth across it. Backus argued that that "Von Neumann bottleneck" of not being able to access program and data at the same time ought to be done away with somehow in his "Can Programming Be Liberated From The Von Neumann Style" http://www.stanford.edu/class/cs242/readings/backus.pdf http://www.stanford.edu/class/cs242/readings/backus.pdf
- palish 15y agoI... wish I understood. I'm just a lowly Blub programmer. An executable is often less than 1MB, and certainly always less than 100MB. In contrast, a 14GB video game still loads pretty quickly, and the data that goes across the bus per frame is often a couple orders of magnitude larger than the program executable itself. I know I'm missing something obvious...
- modeless 15y agoThe Von Neumann architecture refers to the idea of a computer that has a CPU with a separate memory which stores both programs and data (as pretty much all computers do today). In this type of system the bus between memory and CPU becomes a bottleneck. A non-Von-Neumann architecture might look more like the brain, which doesn't have a CPU at all, but instead colocates processing with memory, eliminating the "memory bus" bottleneck and enabling massive parallelism.
- InclinedPlane 15y agoModern computers are extremely fast, and can still do tremendous amounts of computations despite the limitations of the Von Neumann architecture. But make no mistake, the Von Neumann bottleneck is a serious and fundamental problem. The CPU has to spend a lot of effort shuttling data back and forth. Worse yet, it has to spend a lot of time waiting on data (swapping to/from disk, for example). Even when you're CPU is at 100% utilization the vast majority of cycles are spent doing nothing but waiting. That has huge ramifications, affecting everything from performance to power efficiency, etc. Consider a typical snippet of CPU's life. The next instruction is read from memory, it tells the CPU to move a value from memory into a register. The next instruction after that is read from memory, it tells the CPU to move a different value from memory into a different register. The next instruction is read from memory, it tells the CPU to do some operation with the values in those two registers. The next instruction is read from memory, it tells the CPU to test whether the result from the previous instruction is 0, if it was then jump to a specific address. Since it was the CPU fetches the next instruction from that location in memory. And so on. It only takes following this process for a little while to see how tedious it is. We've managed to significantly improve it by adding fast local memory caches to the CPU but even if the memory operated at the speed of the CPU it would still be inefficient. Now, imagine if instead of megabytes of low latency cache you have gigabytes. Now, imagine if instead of having a low latency cache at all the processor is directly wired to the RAM as if the RAM was just a large collection of registers. Instead of "fetch me X, fetch me Y, add X + Y, put the result back to Z" all of that could be a single CPU instruction. Moreover, it would be far, far rarer for the CPU to be waiting for data merely due to local latency. This would improve the effective computing power and power efficiency of CPUs by several orders of magnitude. The impact it would have on computing is truly mind boggling. Let me express it in a different way. Imagine if your cell phone had the same raw computing power as a top of the line GPU does today, with the same battery life and with the same transistor count and clock speed on the CPU, just with a different architecture and different RAM.
- nwatson 15y agoThe bad side-effects of this memory technology: you can't just power-off your computer to hide your current activity; decrypted passwords in memory still will be readable after shutoff.
- jasonwatkinspdx 15y agoThis is silly. Just because memory is non volatile storage doesn't mean the OS can't do reasonable things like clearing out some state as it goes to sleep.
- nwatson 15y agoOk. So your computer is in lock-screen mode requiring you to enter a password before resuming your interactive session. Someone with physical access to your computer certainly can find a way to divorce the memory from the rest of the system without letting the OS do its thing ... your live program memory is compromised. This memory often will have more sensitive info than your (possibly encrypted) mass storage.
- hetman 15y agoThis is already possible with existing DRAM memory; simply cool the RAM chips sufficiently and you increase data retention enough to extract the RAM sticks and read back the data. However, if someone has physical access to your PC, there is almost certainly an easier way for them to gain access to your data. The best protection is restricting physical access.
- jasonwatkinspdx 15y agoI disagree. Firstly, the fabrication process everyone is excited about puts the memrister cells directly atop the cmos logic gates as just another layer to the die. No external memory bus to tap into. So you'd need the sort of equipment used to remove layers from dies to expose the cells for reverse engineering, testing, etc. If someone with these resources is after you, you're already fucked regardless of the exact technological vector. Secondly, a system designer could trivially add some amount of volatile storage for holding security sensitive data. Various schemes of encrypted pages that are decrypted using a key stored in volatile SRM within the CMS could be used. In other words, we could do the same things we currently do with hard drives between the memrister array and SRAM that acts as a decrypted cache. Thirdly, you're applying an expectation to all memristers that is not applied to existing storage technologies. It might be a fair criticism of a concrete product that operates in an insecure way, but it's absurd to apply this expectation to an entire technology.
- rbanffy 15y agoHere we have HP on the verge of profoundly transforming our industry and a CEO (who should be aware of this) wanting to turn the company into an SAP, because that's the future... I hope Meg Whitman does better than Leo Apotheker. Shouldn't be hard.
- vnchr 15y agoBut will Meg take it in the right direction either? Her experience is consumer-facing... I hope there is an empowered VP or 2 who will make that initiative a success.
- rbanffy 15y agoI think the greatest impact of the memristor is in the consumer space. When you have a 1000-fold (or million-fold) quantitative change you are bound to have a qualitative change as well... What would a computer with petabytes of non-volatile RAM look like? How would you package software for it? Will it reboot from time to time? What does a reboot mean when your memory is non-volatile? I have my hunches, but the effort to find answers to my few questions is dwarfed by the effort to find out what the relevant questions will be in this brave new world and if we can answer them. Or even understand them.
- rsanchez1 15y agoA memristor TouchPad would've been really hot. I wonder how these theoretical projects will survive in an HP that is only concerned with how much profit each project makes to appease shareholders...